1. Technical Field
The embodiments described herein relate to a phase-change memory device and a method of fabricating the same and, more particularly, to a phase-change memory device including a phase-change layer with improved deposition property and a method of fabricating the same.
2. Related Art
As IT technologies develop, demand for next generation semiconductor memory devices with ultra-high speed and large capacity, which are suitable for portable information communication systems and appliances, increases. It is desirable that the next generation semiconductor memory devices have the non-volatile properties of flash memory devices, the high speed operation of static random access memories (SRAMs), and the high integration degree of dynamic RAMs (DRAMs), while achieving a lower power consumption. As the next generation semiconductor memory devices, ferroelectric RAMs (FRAMs), magnetic RAMS (MRAMs), phase-change RAMs (PRAMs) or nano floating gate memories (NFGMs), which have lower power consumption and excellent data retention and write/read characteristics as compared with conventional memory devices, have been researched. Among these next generation semiconductor memory devices, as the PRAMS having a simple structure can be fabricated at a lower cost and operate at a high speed, the PRAMs are being heavily studied.
The PRAM includes a phase-change layer of which a crystal state is changed depending on the heat produced by an applied current. A chalcogenide (GST) based material which is comprised of germanium (Ge), antimony (Sb) and tellurium (Te) is typically used as the phase-change layer of the PRAM. The crystal state of the phase-change layer such as a GST layer is changed by the heat produced according to an intensity of a supplied current and a current supply time. The phase-change layer has a higher resistivity at an amorphous state and a lower resistivity at a crystalline state such that it may be used as a data storage medium of a memory device.
The phase-change layer is easily changed from the amorphous state to the crystalline state due to its crystallization characteristic. However, the conversion from the crystalline state to the amorphous state may consume a large amount of current. The current for the phase-change layer in converting from the crystalline state to the amorphous state is called as a reset current. Methods for reducing the reset current in the PRAM have been suggested.
The method of forming the phase-change layer in a confined structure has been suggested to reduce the reset current. The phase-change layer is buried within a phase-change area of a hole type in the confined structure to improve phase-change efficiency, thus reducing the reset current.
However, in order to deposit the phase-change layer of the confined structure, the phase-change layer is to have selectivity with respect to the deposition. As known, the GST layer which is a typical phase-change layer has a high deposition selectivity. Accordingly, when the GST layer is applied to the confined structure, the GST layer may not be uniformly deposited within the hole, and thus it is difficult to fill the hole with the GST layer. Accordingly, the phase-change layer may not be uniformly formed within the phase-change area to cause a void such as a seam or an open fail.